Early technology node manufacturability is limited by yield loss due to high defect densities. Defects can result in immediate yield loss as well as downstream reliability issues. Heuristic yield analysis comprising the application of test patterns to an integrated circuit allows for observation of defects. However, diagnosis of a failure mode associated with a respective defect is a challenge as the location of the defect is difficult to determine. Often physical failure analysis is required to locate a defect and identify a failure mode.